14 #ifndef ATOMIC_PRV_PPC_H_
15 #define ATOMIC_PRV_PPC_H_
18 inline void readBarrier() {
19 asm volatile(
"isync" :::
"memory" );
21 inline void writeBarrier() {
22 asm volatile(
"osync" :::
"memory" );
24 inline void memoryBarrier() {
25 asm volatile(
"sync" :::
"memory" );
28 inline void pauseN(
unsigned int cnt) {
29 for(
unsigned int i = cnt; i != 0; --i)
30 asm volatile(
"nop" :::
"memory" );
33 #define MAX_SIZEOF_CAS SIZEOF_VOID_P
36 inline bool atomicCompareAndSet(T oldv, T newv, T *target ) {
38 asm volatile (
"1: \n"
39 "lwarx %[ret], 0, %[target] \n"
40 "cmpw %[ret], %[oldv] \n"
42 "stwcx. %[newv], 0, %[target] \n"
46 : [oldv]
"r" (oldv), [newv]
"r" (newv), [target]
"r" (target)
52 inline T atomicSwap(T newv, T *target ) {
54 asm volatile (
"1: \n"
55 "lwarx %[ret], 0, %[target] \n"
56 "stwcx. %[newv], 0, %[target] \n"
59 : [newv]
"r" (newv), [target]
"r" (target)
64 inline void atomicInc(T *target ) {
66 asm volatile (
"1: \n"
67 "lwarx %[ret], 0, %[target] \n"
68 "addi %[ret], %[ret], 1 \n"
69 "stwcx. %[ret], 0, %[target] \n"
72 : [target]
"r" (target)
76 inline void atomicDec(T *target ) {
78 asm volatile (
"1: \n"
79 "lwarx %[ret], 0, %[target] \n"
80 "addi %[ret], %[ret], -1 \n"
81 "stwcx. %[ret], 0, %[target] \n"
84 : [target]
"r" (target)
88 inline void atomicAdd(T *target, T x ) {
90 asm volatile (
"1: \n"
91 " lwarx %[ret], 0, %[target] \n"
92 "add %[ret], %[ret], %[x] \n"
93 "stwcx. %[ret], 0, %[target] \n"
96 : [target]
"r" (target), [x]
"r" (x)
100 template <
typename T>
101 inline bool atomicAddAndTest(T *target, T x ) {
103 asm volatile (
"1: \n"
104 "lwarx %[ret], 0, %[target] \n"
105 "add %[ret], %[ret], %[x] \n"
106 "stwcx. %[ret], 0, %[target] \n"
109 : [target]
"r" (target), [x]
"r" (x)
114 template <
typename T>
115 inline bool atomicDecAndTest(T *target ) {
116 return atomicAddAndTest(target, (T)-1);